Table of Contents
Advertisement
ESMT
6. Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
C L K
C M D
W R
D Q
D 0
D 1
.
7. Auto Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
C L K
C M D
W R
D Q
D 0
D 1
*Note : 1. t
: Last data in to row precharge delay.
RDL
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after t
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
P R E
D 3
D 2
t
R D L
* N o t e 1
D 2
D 3
t
R D L ( m i n )
* N o t e 3
A u t o P r e c h a r g e s t a r t s
2 ) N o r m a l R e a d ( B L = 4 )
C L K
C M D
R D
D Q ( C L 2 )
C M D
D Q ( C L 3 )
2 ) N o r m a l R e a d ( B L = 4 )
C L K
C M D
R D
D Q ( C L 2 )
D Q ( C L 3 )
from this point.
RP
M12L64164A
P R E
C L = 2
* N o t e 2
Q 3
Q 0
Q 1
Q2
P R E C L = 3
* N o t e 2
Q3
Q 0
Q 1
Q2
D 0
D 2
D 3
D 1
D 0
D 1
D 2
* N o t e 3
A u t o P r e c h a r g e s t a r t s
Publication Date: May 2008
Revision: 3.3
D 3
22/46
Advertisement
Table of Contents
