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ESMT
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
C L O C K
C K E
C S
t
R C D
R A S
C A S
A D D R
R a
BA1
A 1 0 / A P
R a
C L = 2
D Q
C L = 3
W E
D Q M
Row Active
( A - Bank )
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid
bus contention.
2. Row precharge will interrupt writing. Last data input , t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
3
4
5
6
7
C a
C b
Q a 0
Q a 1
Q b 0
Q a 0
Q a 1
Read
Read
( A - Bank )
( A - Bank )
8
9
10
11
12
H I G H
C c
D c 1
Q b 1
Q b 2
D c 0
Q b 0
Q b 1
D c 1
D c 0
t
C D L
* N o t e 1
Write
( A - Bank )
before row precharge , will be written.
RDL
M12L64164A
13
14
15
16
* N o t e 2
C d
t
R D L
D d 0
D d 1
D d 0
D d 1
* N o t e 3
Write
P r e c h a r g e
( A - Bank )
( A - B a n k )
: D o n ' t C a r e
Publication Date: May 2008
Revision: 3.3
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