Table of Contents
Advertisement
ESMT
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
C L O C K
C K E
C S
t
R C D
R A S
C A S
A D D R
R a
B A 0
B A 1
A 1 0 / A P
R a
C L = 2
D Q
C L = 3
W E
D Q M
Row Active
( A - Bank )
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
available after Row precharge. Last valid output will be Hi-Z (t
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
3
4
5
6
7
* N o t e 2
C b
C a 0
Q a 0
Q a 1
Q a 0
Precharge
Read
( A - Bank )
( A - Bank )
8
9
10
11
12
H I G H
R b
R b
Q a 2
Q a 3
* N o t e 3
Q a 1
Q a 2
Q a 3
* N o t e 3
Row Active
( A - Bank )
) after the clock.
SHZ
M12L64164A
13
14
15
16
17
C b 0
Q b 0
Q b 1
Q b 2
Q b 3
Q b 0
Q b 1
Q b 2
Q b 3
t
Write
( A - Bank )
: D o n ' t C a r e
Publication Date: May 2008
Revision: 3.3
18
19
t
R D L
R D L
P r e c h a r g e
( A - B a n k )
32/46
Advertisement
Table of Contents
