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ESMT
8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
C L K
CM D
W R
DQ M
DQ
D 0
2 ) R e a d B u r s t S t o p ( B L = 4 )
CL K
C M D
RD
DQ ( C L 2 )
D Q ( C L 3 )
9. MRS
1 ) M o d e R e g i s t e r S e t
C L K
C M D
*Note:
1. t
: 1 CLK ; Last data in to burst stop delay.
BDL
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
3. Write burst is terminated. t
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying t
6. PRE : All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
Elite Semiconductor Memory Technology Inc.
S T O P
D 3
D1
D2
D 4
D5
* N o t e 1
t
B D L
S T O P
* N o t e 2
Q 0
Q 1
* N o t e 2
Q 0
Q 1
*N o t e 6
P R E
M RS
t
R P
2 C L K
determinates the last data write.
RDL
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
CM D
W R
t
DQ M
DQ
D 0
D1
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
CL K
C M D
R D
D Q ( C L 2 )
D Q ( CL 3 )
A C T
min delay) with DQM.
RAS
M12L64164A
* N o t e 3
P R E
R D L
* N o t e 4
M a s k M a s k
* N o t e 5
P R E
Q 0
Q 1
Q 2
Q 3
Q 3
Q 1
Q 0
Q 2
Publication Date: May 2008
Revision: 3.3
23/46
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