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ESMT
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
C L O C K
C K E
C S
R A S
C A S
A D D R
R A a
BA0
BA1
A 1 0 / A P
R A a
C L = 2
D Q
C L = 3
W E
D Q M
Row Active
(A-Bank)
*Note : 1. t
should be met to complete write.
CDL
Elite Semiconductor Memory Technology Inc.
3
4
5
6
7
R D b
C A a
R B b
Q A a 1 Q A a 2 Q A a 3
Q A a 0
Q A a 1 Q A a 2 Q A a 3
Q A a 0
Read
Precharge
(A-Bank)
(A-Bank)
Row Active
(D-Bank)
8
9
1 0
1 1
1 2
H I G H
C D b
D D b 0
D d b 1 D D b 2 D D d 3
D d b 1 D D b 2 D D d 3
D D b 0
W r i t e
( D - B a n k )
Row Active
(B-Bank)
M12L64164A
1 3
1 4
1 5
1 6
1 7
R B c
C B c
R A c
* N o t e 1
t
C D L
R e a d
( B - B a n k )
Publication Date: May 2008
Revision: 3.3
1 8
1 9
Q B c 0 Q B c 1 Q B c 2
Q B c 0 Q B c 1
: D o n ' t C a r e
36/46
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