Hyundai H-HT5115-N Service Manual page 103

ESMT
12. About Burst Type Control
Sequential Counting
Basic
MODE
Interleave Counting
Random Random Column Access
MODE t
CCD
13. About Burst Length Control
1
2
Basic
MODE
4
8
Full Page
Random
Burst Stop
MODE
RAS Interrupt
(Interrupted by
Precharge)
Interrupt
MODE
CAS Interrupt
Elite Semiconductor Memory Technology Inc.
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
= 1 CLK
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
At MRS A210 = "000"
At auto precharge . t
At MRS A210 = "001"
At auto precharge . t
At MRS A210 = "010"
At MRS A210 = "011"
At MRS A210 = "111"
At the end of the burst length , burst is warp-around.
t = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
BDL
Using burst stop command, any burst length control is possible.
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
t = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
RDL
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
should not be violated.
RAS
should not be violated.
RAS
M12L64164A
Publication Date: May 2008
Revision: 3.3 25/46