Table of Contents
Advertisement
ESMT
Self Refresh Entry & Exit Cycle
0
1
2
C L O C K
* N o t e 1
C K E
t
S S
C S
R A S
C A S
A D D R
B A 0 , B A 1
A 1 0 / A P
D Q
W E
D Q M
S e l f R e f r e s h E n t r y
* Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum t
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
is required after CKE going high to complete self refresh exit.
RFC
7. Burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
Elite Semiconductor Memory Technology Inc.
3
4
5
6
* N o t e 2
* N o t e 3
H i - Z
7
8
9
10
11
* N o t e 4
* N o t e 5
H i - Z
S e l f R e f r e s h E x i t
is required before exit from self refresh.
RAS
M12L64164A
12
13
14
15
16
t
m i n
R F C
* N o t e 6
* N o t e 7
A u t o R e f r e s h
Publication Date: May 2008
Revision: 3.3
17
18
19
: D o n ' t c a r e
42/46
Advertisement
Table of Contents
