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Revisions List
Revision No Description
A
Preliminary draft
B
1. Correct the extra OTP sector from 256 bytes to 512 bytes on page 1
and 22.
2. Correct the OTP sector is mapping to sector from 255 to 511 on page
22.
3. Update the Table 6. Status Register Bit Locations on page 12.
4. Modify the Figure 17 on page 20 for the starting point of
5. Modify the Figure 18 on page 21
(1) revise the manufacture ID to 1Ch
(2) the number of clock count to cover the manufacture ID should be
31 to 38 and the last clock to clock out device ID is 46.
6. Modify the Figure 19 in page 22, the clock count to cover the device ID
should be from 15 to 31
7. Change Table 10. 100MHz AC Characteristics t
on page 25
C
Remove C grade option of temperature range on page 1 and page 34
D
1. Add Eon products' New top marking "cFeon" information on page 1.
2. Add the description "Serial Interface Architecture "and modify active
current (typical) from 5mA to 12mA on page 2.
3. List the Note 4 for 90h command in Table 4 on page 12.
4. Update Table 6. Status Register Bit Locations on page 13.
5. Add Table 7. OTP Sector Address on page 23.
6. Add Note " Vcc (max) is 3.6V and Vcc (min) is 2.7V " in Table 8 on
page 24.
7. Modify I CC3 from "Q = open" to " DQ = open " in Table 9 on page 25
8. Correct the typo "tCLH to tCH" 、 "tCLL to tCL"、"tHHQZ to tHHQX" in
Table 11 and Table 12 on page 26 and 27.
9. Modify Storage Temperature from "-65 to + 125" to "-65 to +150"
on page 29
10.Delete Latch up Characteristics Table from version C.
11.Modify official name from 209mil to 208mil and delete dimension " c "
in Figure 26 on page 31.
12. Modify Figure 28. VDFN8 ( 5x6mm ) dimension A from 0.80 to 0.75
on page 32.
E
1. Update Page program, Sector erase and Block erase time parameter
on page2, 26 and 27.
2. Modify Icc4, Icc5, Icc6 and Icc7 on page 25.
F
1 Modify Chip erase time (typical) from 18 s to 7s on page 2 and 25
2. Change OTP security sector from 512 byte to 128 byte and update
table 7 on page 2 and 22.
3. Remove the Protected Area Sizes definition of BP2、BP1 and BP0 =
001 to 110 in table 3 on page 9.
4. Remove 16 pin SOP 300mil package information from version E
5. Remove speed 75MHz information from version E.
6. Update the VDFN package (D2 from 4.23mm to 3.4mm) on page 30
and 32.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
33
©2004 Eon Silicon Solution, Inc.,
Rev. F, Issue Date: 2009/03/16
t
RES2
from 6 ns to 8 ns
CLQV
www.eonssi.com
EN25F16
Date
2007/05/02
2008/03/10
2008/06/23
2008/12/18
2009/01/20
2009/03/16
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