Table of Contents
Advertisement
Specifications are subject to change without notice
XTALI
YUV[7:0]
HSYNC
VSYNC
9-10 SPDIF I/O Interface
BCK negative edge to ASDATA valid
ASDATA/LRCK input setup
ASDATA/LRCK input hold
ASDATA/LRCK
SPLIN_BCK
ASDATA/LRCK
(input)
t1
t2
YUV[7:0]
t3
Digital Video Output Interface Timing Diagram
Parameter
BCK
SPDIF Input/Output Timing Diagram
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
YUV[7:0]
t5
Symbol
Min
Typ
T1
1.0
T2
T3
1.2
ASDATA/LRCK
t3
t2
ASDATA/LRCK
ASDATA/LRCK
28
Max
Units
3.0
ns
3.0
ns
ns
Advertisement
Table of Contents
