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ESMT
AC OPERATING TEST CONDITIONS
PARAMETER
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Output
Ω
870
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
Row cycle time
@ Auto refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid
Output data
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
Elite Semiconductor Memory Technology Inc.
(VDD = 3.3V ± 0.3V ，TA = 0 to 70 C
3.3V
Ω
1200
V
(DC) =2.4V , I
OH
V
(DC) =0.4V , I
OL
50pF
SYMBOL
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC(min)
t
RFC(min)
t
CDL(min)
t
RDL(min)
t
BDL(min)
t
CCD(min)
CAS latency = 3
CAS latency = 2
after self refresh exit.
RFC
VALUE
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
= -2 mA
OH
Output
= 2 mA
OL
VERSION
-5
-6
10
12
15
18
15
18
38
40
100
53
58
55
60
1
2
1
1
2
1
M12L64164A
° )
Ω
Z0 =50
(Fig. 2) AC Output Load Circuit
UNIT
-7
14
ns
20
ns
20
ns
42
ns
us
63
ns
70
ns
CLK
CLK
CLK
CLK
ea
Publication Date: May 2008
Revision: 3.3
UNIT
V
V
ns
V
Vtt = 1.4V
Ω
50
50pF
NOTE
1
1
1
1
1
1,5
2
2
2
3
4
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