Table of Contents
Advertisement
ESMT
Page Write Cycle at Different Bank @ Burst Length = 4
0
1
2
C L O C K
C K E
C S
R A S
C A S
A D D R
R A a
R B b
B A 0
B A 1
R A a
R B b
A 1 0 / A P
D Q
W E
D Q M
R o w A c t i v e
( A - Bank )
R o w A c t i v e
( B - B a n k )
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
3
4
5
6
7
C A a
C B b
D A a 0
D A a 3
D A a 1
D A a 2
D B b 0 D B b 1
t
C D L
W r i t e
W r i t e
( B - B a n k )
( A - B a n k )
R o w A c t i v e
8
9
10
11
H I G H
R C c
C C c
R D d
R C c
R D d
D C c 0 D C c 1
D B b 2
D B b 3
R o w A c t i v e
( D - B a n k )
W r i t e
( C - B a n k )
( C - B a n k )
M12L64164A
12
13
14
15
16
C D d
D D d 0 D D d 1
C D d 2
t
R D L
* N o t e 1
W r i t e
P r e c h a r g e
( D - B a n k )
( A l l B a n k s )
Publication Date: May 2008
Revision: 3.3
17
18
19
* N o t e 2
: D o n ' t c a r e
35/46
Advertisement
Table of Contents
