Dram Latency; Figure 3-2. Memory Block Diagram - Motorola MVME2301 Installation And Use Manual

Block Diagram
3

DRAM Latency

3-8
There are one or two blocks of DRAMs that provides 16M/32M or
64M/128M of ECC DRAM. The DRAM blocks consists of 9 devices
each. Either 1Mx16 (Page) 50-pin TSOPII DRAM or 4Mx16 (EDO)
50-pin TSOPII DRAM are used to provide 16/32/64/128M. When
populated, these blocks appears as Block A and Block B to the
Falcon chipset.
Refer to the MVME2300-Series VME Processor Module ProgrammerÕs
Reference Guide for additional information and programming
details.
The block diagram for the memory interface is shown in the
following figure:
Memory Controller
Falcon Chipset
Buffers

Figure 3-2. Memory Block Diagram

The ECC memory access latency times for 60ns, fast page DRAMs
are shown in the following table.
ECC DRAM
16M to 128M
FLASH
3M to 5M
Buffers
Buffers