Prestigio CAVALIERE 141 Technical & Service Manual page 9

Prestigio Cavaliere 141 Technical Service Manual
The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator
with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to
deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to SiS 301B Video Bridge
packaged in 100-pin PQFP is incorporated to expand the SiS 650 functionality to support the secondary display, in
addition to the default primary CRT display. The SiS 301B Video Bridge integrates an NTSL/PAL video encoder
with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear scaling capability for TFT
LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the
extended secondary display (TV, TFT LCD Panel, 2'nd CRT) features the Dual View Capability in the sense that
both can generate the display in independent resolutions, color depths, and frame rates.
Two separate buses, Host-t-GUI in the width of 64 bits, and GUI-t-Memory Controller in the width of 128 bits are
devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266 memory
subsystem, the 128 bits GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate,
respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and
the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP
controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of
dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous
downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb
the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data
queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-
data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to
utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data
requests streamlines in the foreground.
8