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Prestigio Cavaliere 141
The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
specific application. In addition, the SiS961 supports Deeper Sleep power state for Intel Mobile processor. For AMD
processor, the SiS961 use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.
A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS645DX and SiS961 MuTIOL
Media I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Channels Layer
delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to
Multi-threaded I/O Channels layer, the Multi-threaded I/O Packet Layer in SiS961 to transfer data w/ 533 MB/s
bandwidth from/to Multi-threaded I/O Channels layer to/from SiS645DX, and the Multi-threaded I/O Packet Layer
in SiS645DX to transfer data w/ 533 MB/s from/to memory sub-system to/from the Multi-threaded I/O Packet Layer
in SiS961.
Features
Meet PC2001 Requirements
High performance SiS MuTIOL Technology Interconnecting SiS North Bridge and South Bridge
chips
Bi-directional 16-bit data bus
533MB/s performance in 4x66 MHz mode
Distributed Arbitration Scheme
Supports Back to Back Transaction
Integrated Multi-threaded I/O link ensures concurrency of upstream/down stream data
transfer
with 1.2GB/s bandwidth
16
Technical Service Manual
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