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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Pin Name
Type/No.
DSTBP[3:0]#
Input/
Data strobe used to latch in D[63:0]#.
Output
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DRDY#
Input/
DRDY# (Data Ready) is asserted by the data driver on each data
Output
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of all processor system
bus agents.
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/ PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/ PBE#
is similar to the ERROR# signal on the INTEL 387 coprocessor, and
is included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending
break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will
remain asserted until STPCLK# is deasserted. For additional
information on the pending break event functionality, including the
identification of support of the feature and enable/disable information,
refer to volume 3 of the Intel Architecture Software Developer's
Manual and the Intel Processor Identification and the CPUID
Instruction application
note.
GHI#
Input
The GHI# signal controls the selection of the operating mode bus
ratio and voltage in the Mobile Intel Pentium 4 Processor-M. On the
Mobile Intel Pentium 4 Processor-M featuring Enhanced Intel
SpeedStep technology, this signal is latched on entry to Sleep state
and is observed during the Deep Sleep state. GHI# determines which
of two performance states is selected for operation. This signal is
ignored when the processor is not in the Deep Sleep state. This signal
should be driven with an Open-drain driver. For connection and
termination guidelines refer to the Mobile Intel.Pentium.4
Processor-M and Intel.845MP/845MZ Chipset Platform Design
Guide.
Descr iption
Signals
Associated Str obe
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
Pin Name
Type/No.
GTLREF
Input
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCC. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1. Refer to
the Mobile Intel. Pentium. 4 Processor-M and Intel. 845MP/845MZ
Chipset Platform Design Guide for more information.
COMP[1:0]
Analog
COMP[1:0] must be terminated on the system board using precision
resistors.Refer to the Mobile Intel. Pentium. 4 Processor-M and Intel.
845MP/845MZ Chipset Platform Design Guide for details on
implementation.
HIT#
Input/
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
HITM#
Output
snoop operation results. Any system bus agent may assert both HIT#
Input/
and HITM# together to indicate that it requires a snoop stall, which
Output
can be continued by reasserting HIT# and HITM# together.
IERR#
Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor system bus. This
transaction may optionally be converted to an external error signal
(e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#.
This signal does not have on-die ter mination and must be
ter minated on the system boar d.
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol
floating-point instructions. If IGNNE# is deasserted, the processor
generates an exception on a noncontrol floating-point instruction if a
previous floating-point instruction caused an error. IGNNE# has no
effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on Reset
vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal and must connect the appropriate pins of all
processor system bus agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
76
Technical Service Manual
Descr iption
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