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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Pin Name
Type/No.
ITPCLKOUT
Output
ITPCLKOUT[1:0] is an uncompensated differential clock output that
1:0]
is a delayed copy of the BCLK[1:0], which is an input to the
processor. This clock output can be used as the differential clock into
the ITP port that is designed onto the motherboard. If
ITPCLKOUT[1:0] outputs are not used, they must be terminated
properly. Refer to the ITP700 Debug Port Design Guide for details on
implementing a debug port.
ITP_CLK[1:0]
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects in the system. These are not
processor signals.
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward compatible with the signals of those names on the Pentium
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default
after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK#
Input/
LOCK# indicates to the system that a transaction must occur
Output
atomically. This signal must connect the appropriate pins of all
processor system bus agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor system bus, it will wait until it observes LOCK#
deasserted. This enables symmetric agents to retain ownership of the
processor system bus throughout the bus locked operation and ensure
the atomicity of lock.
REQ[4:0]#
Input/
REQ[4:0]# (Request Command) must connect the appropriate pins of
Output
all processor system bus agents. They are asserted by the current bus
owner to define the currently active transaction type. These signals
are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal
description for details on parity checking of these signals.
Descr iption
Pin Name
Type/No.
MCERR#
Input/
MCERR# (Machine Check Error) is asserted to indicate an
Output
unrecoverable error without a bus protocol violation. It may be driven
by all processor system bus agents.
MCERR# assertion conditions are configurable at a system level.
Assertion options are defined by the following options:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus
transaction after it observes an error.
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, please refer to
the IA-32
Software Developer's Manual, Volume 3: System Programming
Guide.
PROCHOT#
Output
The assertion of PROCHOT# (Processor Hot) indicates that the
processor die temperature has reached its thermal limit. See Section 6
for more details.
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and power
supplies are stable and within their specifications. 'Clean' implies that
the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on
until they come within specification. The signal must then transition
monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It should
be driven high throughout boundary scan operation.
RESET#
Input
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at least
one millisecond after VCC and BCLK have reached their proper
specifications. On observing active RESET#, all system bus agents
will deassert their outputs within two clocks. RESET# must not be
kept asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration.
This signal does not have on-die ter mination and must be
ter minated on the system boar d.
77
Technical Service Manual
Descr iption
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