Prestigio CAVALIERE 141 Technical & Service Manual page 8

Prestigio Cavaliere 141 Technical Service Manual
1.2.3 SiS650 IGUI HMAC 3D Graphic DDR/SDR Chipset
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a
high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS
MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO.
SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die
termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support maximum
outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and
Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems.
It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from
the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated
GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A
high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS650 and SiS961 MuTIOL Media
I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Link Layer delivering
1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-
threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s
bandwidth from/to Multi-threaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder
in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high
performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or
external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by
retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the
Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the
frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
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