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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
MuTIOL Connect Inter face
Name
Pin Attr
ZCLK
I
Megaband I/O Connect Clock
3.3V - M
ZUREQ
I/O
Megaband I/O Conect Controll pins
1.8V - M
ZDREQ
I/O
Megaband I/O Conect Controll pins
1.8V - M
ZSTB[1:0]
I/O
Megaband I/O Connect Strobe
1.8V - M
ZSTB[1:0]#
I/O
Strobe Compliment
1.8V - M
ZAD[15:0]
I/O
Address/Data pins
1.8V - M
ZVRE
I -M
Megaband I/O Connect I/O reference voltage
ZCMP_N
I -M
N-MOS Compensation Input
ZCMP_P
I -M
P-MOS Compensation input
Gener al Pur pose I/O
Signal Name
Pin Attr
GPIO[6:0]
I/O
GPIO:
3.3V/5V -M
Can be a general purpose input or output.
GPIO14,[12:7]
I/O
GPIO :
3.3V/5V -AUX
Can be a general purpose input or output.
GPIO13
O
GPO:
3.3V/5V - AUX
Can be a general purpose output.
GPIO[18:15]
O
GPO:
3.3V/5V - AUX
Can be a general purpose output.
GPIO[20:19]
I/O
GPIO:
3.3V/5V - AUX
Can be a general purpose input or output.
Signal Descr iption
Signal Descr iption
Host Bus Inter face
Name
Pin Attr
FERR#
I
Floating Point Er r or :
1.1V/2.65V -M
CPU will assert this signal upon a floating point error occurring.
IGNNE#
OD
Ignor e Numer ic Er r or :
1.1V/2.65V -M
IGNNE# is asserted to inform CPU to ignore a numeric error.
NMI
OD
Non-Maskable Inter r upt:
1.1V/2.65V -M
A rising edge on NMI will trigger a non-maskable interrupt to
CPU.
INTR
OD
Inter r upt Request:
1.1V/2.65V -M
High-level voltage of this signal conveys to CPU that there is
outstanding interrupt(s) needed to be serviced.
APICD[1:0]
I/OD
APIC Data:
1.1V/2.65V -M
These two signals are used to send and receive APIC data.
CPUSLP#/
OD
CPU Sleep:
CPUSTP#
1.1V/2.65V -M
The CPUSLP# can be used to force CPU enter the Sleep state.
CPU Clock STOP:
For Intel Mobile processor, this signal can be used to stop the
clock to the processor. If the processor is in Quick Start state
and the processor clock is stopped, the processor will enter the
Deep Sleep state.
For AMD processor, this signal can be to reduce processor
voltage during C3/S1 state.
STPCLK#
OD
Stop Clock:
1.1V/2.65V -M
STPCLK# will be asserted to inhibit or throttle CPU activities
upon a pre-defined power management event occurs
INIT#
OD
Initialization:
1.1V/2.65V -M
INIT is used to re-start the CPU without flushing its internal
caches and registers. In Pentium III platform it is active high.
This signal requires an external pull-up resistor tied to 3.3V.
APICCK
I
APIC Clock:
2.5V - M
This signal is used to determine when valid data is being sent
over the APCI bus.
A20M#
OD
Address 20 Mask:
1.1V/2.65V- M
When A20M# is asserted, the CPU A20 signal will be
forced to "0"
84
Technical Service Manual
Signal Descr iption
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