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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
SiS MuTIOL Inter face
Name
Pin Attr
PIPE#
I
AGP Pipeline Request
1.5V/3.3V - M
SBA[7:0]
I/O
Side Band Address
1.5V/3.3V - M
RBF#
I
Read Buffer Full
1.5V/3.3V - M
WBF#
I
Write Buffer Full
1.5V/3.3V - M
AD_STB[1:
I/O
AD Bus Strobe
0]
1.5V/3.3V - M
AD_STB[1:
I/O
AD Bus Strobe Compliment
0]#
1.5V/3.3V - M
SB_STB
I
Side Band Strobe
1.5V/3.3V - M
SB_STB#
I
Side Band Strobe Compliment
1.5V/3.3V - M
Ster eo Glasses Inter face
Na m e
Pin Attr
CSYNC
O
Stereo Clock
3.3V - M
RSYNC
O
Stereo Right
3.3V - M
LSYNC
O
Stereo Left
3.3V - M
Signal Descr iption
Sign a l De scr iption
Test Mode/Har dwar e Tr ap/Power Management
Na m e
Pin Attr
DLLEN#
I/O
Hardware T rap pin (refer to section 5)
3.3V/5V - M
DRAM_SEL
I
Hardware T rap pin (refer to section 5)
3.3V/5V - AUX
T RAP[1:0]
I
Hardware T rap pins (refer to section 5)
3.3V/5V - M
ENT EST
I
T est Mode enable pin
3.3V/5V - M
T EST MOD
I
T est Mode select pin
E[2:0]
3.3V/5V - M
Nand T ree T est: 100
AUXOK
I
Auxiliary Power OK :
3.3V - AUXI
T his signal is supplied from the power source of resume well. It
is also used to reset the logic in resume power well. If there is
no auxiliary power source on the system, this pin should be tied
together with PWROK.
PCIRST #
I
PCI Bus Reset :
3.3V - AUXI
PCIRST # is supplied from SiS MuT IOL Media IO SiS961.
PWROK
I
Main Power OK :
3.3V - AUXI
A high-level input to this signal indicates the power being
supplied to the system is in stable operating state. During the
period of PWROK being low, CPURST and PCIRST # will all
be asserted until after PWROK goes high for 24 ms.
82
Technical Service Manual
Sign a l De scr iption
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