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Prestigio Cavaliere 141
Technical Service Manual
Dynamic Clock Enable (CKE) control placing the SDRAM into Suspend to DRAM state
High performance unified memory controller optimizing the DRAM bus utilization
Programmable frame buffer size from 8MB and up to 64MB
128KB SMRAM space re-mapping to A0000h, B0000h, or E0000h
Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
AGP v2.0 Compliant
Supports Graphic Window Size from 4MBytes to 256MBytes
Supports Pipelined Process in CPU-to- A.G.P. Access
Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance A.G.P. Controller
Read/Write Performance
Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to A.G.P. device
Supports Additional AGP4X/2X interface and Fast Write Transaction
High Throughput SiS MuTIOL connect to SiS961 MuTIOL Media I/O
Bi-directional 16 bit data bus
Perform 533MB/s bandwidth in 66MHz x 4 mode
Distributed arbitration strategy with enhanced mode of contiguous DMA data streaming
Packet based, pipelining, and split transaction scheme
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