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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
Power and Gr ound Signals C ontinue
Name
T oler ance
A1XAVDD
3.3V
MAIN
A1XAVSS
0V
GROUND
A4XAVDD
3.3V
MAIN
A4XAVSS
0V
GROUND
AGPVSSREF
0V
GROUND
AUX1.8
1.8V
AUX
AUX3.3
3.3V
AUX
C1XAVDD
3.3V
MAIN
C1XAVSS
0V
GROUND
VGA Inter face
Name
Pin Attr
VOSCI
I
14.318 Reference Clock Input
3.3V - M
HSYNC
O
Horizontal Sync
3.3V - M
VSYNC
O
Vertical Sync
3.3V - M
INTA#
O
Internal VGA Interrupt Pin
3.3V - M
VGPIO[1:0]
I/O
Internal VGA GPIO pins
3.3V - M
VCOMP
AI
Compensation Pin
Analog - M
VRSET
AI
Reference Resistor
Analog - M
VVBWN
AI
Voltage Reference
Analog - M
ROUT
AO
Red Signal Output
Analog - M
GOUT
AO
Green Signal Output
Analog - M
BOUT
AO
Blue Signal Output
Analog - M
Power Plane
T ype Attr ibute
Analog
Analog
Analog
Analog
Analog
Digital
Digital
Analog
Analog
Signal Descr iption
SiS M u T IO L In ter fa ce
Sign a l Na m e
P in Attr
ZCLK
I
SiS M uTIOL Connect
3.3V-M
ZUREQ/ZQREQ I/O
SiS M uTIOL Connect Control pins
1.8-M
ZSTB[1:0]
I/O
SiS M uTIOL Connect Strobe
1.8-M
ZSTB[1:0]#
I/O
Strobe Compliment
1.8-M
ZAD[15:0]
I/O
I/O
1.8-M
1.8V - M
ZVREF
I
SiS M uTIOL Connect Reference Voltage
M
ZCM P_N
I
N-M OS Compensation Input
M
ZCM P_N
I
P-M OS Compensation Input
M
AGPCLK
I
AGP Clock
3.3V – M
AFRAM E#
I/O
AGP Frame#
1.5V/3.3V - M
AIRDY#
I/O
AGP Initiator Ready
1.5V/3.3V - M
ATRDY#
I/O
AGP Target Ready
1.5V/3.3V - M
ASTOP#
I/O
AGP Stop#
1.5V/3.3V - M
ADEVSEL#
I/O
AGP Device Select
1.5V/3.3V - M
ASERR#
I/O
AGP System Error
1.5V/3.3V - M
AREQ#
I/O
AGP Bus Request
1.5V/3.3V - M
AGNT#
I/O
AGP Bus Grant
1.5V/3.3V - M
AAD[31:0]
I/O
AGP Address/Data Bus
1.5V/3.3V - M
AC/BE[3:0
I/O
AGP Command/Byte Enable
1.5V/3.3V - M
APAR
I/O
AGP Parity
1.5V/3.3V - M
ST[2:0]
O
AGP Status Bus
1.5V/3.3V - M
81
Technical Service Manual
Sign a l Descr ip tion
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