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Prestigio Cavaliere 141
Multiple DMA Bus Architecture
Concurrent Servicing of all DMA Devices: Dual IDE Controllers, Two USB 1.1 HC, MAC Controller,
Audio/Modem DMA Controller
Separate 32 Bit Input and Output Data Bus Scheme for each DMA Device
Advanced Performance Merits of Split & Pipelined Transaction and Concurrent
Execution among Multi-I/O Devices
Integrated MuTIOL to PCI Bridge
PCI 2.2 Specification Compliance
Supports up to 6 PCI Masters
Two Prefetch cache Buffers support 2 delayed transactions
Fairness Rotating PCI Arbiter Scheme with Option to Place PCI Master 0 as the Highest Priority
Dual IDE Master/Slave Controller
Integrated Multithreaded I/O Link Mastering with Read Pipelined Streaming
Dual Independent IDE Channels Each with 16 DW FIFO
Native and Compatibility Mode
PIO Mode 0, 1, 2, 3, 4 and Multiword DMA Mode 0, 1, 2
Ultra DMA 33/66/100
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Technical Service Manual
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