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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
H ost BUS In ter fa ce
Na m e
P in Attr
RS[2:0]#
O
Response Status:
1.2~1.85V – M
RS[2:0]# are driven by the response agent to indicate the
transaction response type. The following shows the response
type.
HTRDY#
O
Target Ready:
1.2~1.85V – M
During write cycles, response agent will drive TRDY# to
indicate it is ready to accept data.
DRDY#
I/O
Data Ready:
1.2~1.85V – M
DRDY# is driven by the bus owner whenever the data is valid
on the bus.
DBSY#
I/O
Data Bus Busy:
1.2~1.85V – M
Whenever the data is not valid on the bus with DRDY# is
deserted, DBSY# deasserted to hold the bus.
HD[63:0]#
I/O
Data Bus Busy:
1.2~1.85V – M
Whenever the data is not valid on the bus with DRDY# is
deserted, DBSY# deasserted to hold the bus.
DBI[3:0]#
I/O
Dynamic Bus Inversion: An active DBI# will invert
1.2~1.85V – M
it's corresponding data group signals.
DBI0# is referenced by HD[15:0],
DBI1# is referenced by HD[31:16]
DBI2# is referenced by HD[47:32]
DBI3# is referenced by HD[63:48]
HDSTBP[3:0]#
I/O
Source synchronous data strobe used to latch data at falling edge
1.2~1.85V – M
HD[15:0], DBI0# are latched by HDSTBP0#
HD[31:16], DBI1# are latched by HDSTBP1#
HD[47:32], DBI2# are latched by HDSTBP2#
HD[63:48], DBI3# are latched by HDSTBP3#
HDSTBN[3:0]#
I/O
Source synchronous data strobe used to latch data at falling edge
1.2~1.85V– M
HD[15:0], DBI0# are latched by HDSTBN0#
HD[31:16], DBI1# are latched by HDSTBN1#
HD[47:32], DBI2# are latched by HDSTBN2#
HD[63:48], DBI3# are latched by HDSTBN3#
HNCOM P
I
GTL N-MOS Compensation Input
M
Sign a l Descr ip tion
RS[2:0]
Response
000
Idle State
001
Retry
010
Defer
011
Reserved
100
Reserved
101
No data
110
Implicit Write-back
111
Normal Data
H ost BUS In ter fa ce C on tin u e
Na m e
P in Attr
CPUCLK
I
Host differential clock input.
CPUCLK#
0.71V – M
CPURST#
O
Host Bus Reset:
1.2~1.85V – M
CPURST# is used to keep all the bus agents in
the same initial state before valid cycles issued.
CPUPWRGD#
CPUPWRGD# is used to inform CPU that main power is stable
ADS#
I/O
Address Strobe :
O
1.2~1.85V – M
Address Strobe is driven by CPU or SiS650 to indicate the start
1.2~1.85V – M
of a CPU bus cycle.
HADSTB[1:0]#
Source synchronous address strobe used to latch
1.2~1.85V – M
HREQ[4:0]# & HA[31:3]# at both falling and rising edge.
HREQ[4:0]# & HA[16:3]# are latched by
HASTB0#
HA[31:17] are latched by HASTB1#
HREQ[4:0]#
I/O
Request Command:
1.2~1.85V – M
HREQ[4:0]# are used to define each transaction type during the
clock when ADS# is asserted and the clock after ADS# is
asserted.
HA[31:3]#
I/O
Host Address Bus
1.2~1.85V – M
BREQ0#
O
Symmetric Agent Bus Request:
1.2~1.85V – M
BREQ0# is driven by the symmetric agent to request for the
bus.
BPRI#
O
Priority Agent Bus Request:
1.2~1.85V – M
BPRI# is driven by the priority agent that wants to request the
bus.
BPRI# has higher priority than BREQ0# to access a bus.
BNR#
I/O
Block Next Request:
1.2~1.85V – M
This signal can be driven asserted by any bus agent to block
further requests being pipelined.
HLOCK#
I
Host Lock :
1.2~1.85V – M
CPU asserts HLOCK# to indicate the current bus cycle is
locked.
HIT#
I/O
Keeping a Non-M odified Cache Line
1.2~1.85V – M
HITM #
I/O
Hits a M odified Cache Line:
1.2~1.85V – M
Hit Modified indicates the snoop cycle hits a modified line in
the L1/L2 cache of CPU.
DEFER#
O
Defer Transaction Completion:
1.2~1.85V – M
r defer response to host bus.
79
Technical Service Manual
Sign a l Descr ip tion
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