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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Pin Name
Type/No.
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of all
processor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked
operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BR0#
Input/
BR0# drives the BREQ0# signal in the system and is used by the
Output
processor to request the bus. During power-on configuration this pin
is sampled to determine the agent ID = 0.
This signal does not have on-die ter mination and must be
ter minated.
BSEL[1:0]
Output
BSEL[1:0] (Bus Select) are used to select the processor input clock
frequency. associated with each combination. The required frequency
is determined by the processor, chipset, and clock synthesizer. All
agents must operate at the same frequency. The Mobile Intel Pentium
4 Processor-M operates at a 400-MHz system bus frequency (100
MHz BCLK[1:0] frequency). For more information about these pins,
including termination recommendations refer to the appropriate
platform design guidelines.
D[63:0]#
Input/
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
Output
data pathbetween the processor system bus agents, and must connect
the appropriate pins on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times
in a common clock period. D[63:0]# are latched off the falling edge
of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data
signals correspond to a pair of one DSTBP# and one DSTBN#. The
following table shows the grouping of data signals to data strobes and
DBI#.
Quad-Pumped Signal Gr oups
Data Gr oup
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Furthermore, the DBI# pins determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DBI# signal. When
the DBI# signal is active, the corresponding data group is inverted
and therefore sampled active high.
Descr iption
DSTBN#/
DBI#
DSTBP#
0
0
1
1
2
2
3
3
Pin Name
Type/No.
DBI[3:0]#
Input/
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate
Output
the polarity of the D[63:0]# signals. The DBI[3:0]# signals are
activated when the data on the data bus is inverted. The bus agent will
invert the data bus signals if more than half the bits, within the
covered group, would change level in the next cycle.
DBI[3:0] Assignment To Data Bus
DBR#
Output
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY#
Input/
DBSY# (Data Bus Busy) is asserted by the agent responsible for
Output
driving data on the processor system bus to indicate that the data bus
is in use. The data bus is released after DBSY# is deasserted. This
signal must connect the appropriate pins on all processor system bus
agents.
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or Input/Output agent.
This signal must connect the appropriate pins of all processor system
bus agents.
DP[3:0]#
Input/
DP[3:0]# (Data parity) provide parity protection for the D[63:0]#
Output
signals. They are driven by the agent responsible for driving
D[63:0]#, and must connect the appropriate pins of all Mobile Intel
Pentium 4 Processor-M system bus agents.
DPSLP#
Input
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. In order to
return to the Sleep State, DPSLP# must be deasserted and BCLK[1:0]
must be running.
DSTBN[3:0]#
Input/
Data strobe used to latch in D[63:0]#.
Output
75
Technical Service Manual
Descr iption
Bus Signal
Data Bus Signals
DBI3#
D[63:48]#
DBI2#
D[47:32]#
DBI1#
D[31:16]#
DBI0#
D[15:0]#
Signals
Associated Str obe
D[15:0]#, DBI0#
DSTBN0#
D[31:16]#, DBI1#
DSTBN1#
D[47:32]#, DBI2#
DSTBN2#
D[63:48]#, DBI3#
DSTBN3#
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