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Prestigio Cavaliere 141
5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
AC'97 Inter face
Name
Pin Attr
AC_BIT_CLK
I
AC'97 Bit Clock:
3.3V/5V -M
This signal is a 12.288MHz serial data clock, which is generated
by primary Codec.
AC_RESET#
O
AC'97 Reset:
3.3V -AUX
Hardware reset signal for external Codecs.
AC_SDIN0
I
AC'97 Ser ial Data Input :
3.3V/5V -AUX
Serial data input from primary Codec.
AC_SDIN1
I
AC'97 Ser ial Data Input:
3.3V/5V -AUX
Serial data input from secondary Codec. When Modem Codec is
used, this pin dedicate to Modem Serial data input.
AC_SDIN[3:2]/
I
AC'97 Ser ial Data Input:
GPIO[10:9]
I/O
Serial data input from third and forth Audio Codec.
3.3V/5V -AUX
AC_SDOUT
O
AC'97 Ser ial Data Output:
3.3V -M
Serial data output to Codecs.
AC_SYNC
O
AC'97 Synchr onization:
3.3V -M
This is a 48KHz signal, which is used to synchronize the Codecs
USB Inter face
Name
Pin Attr
USBCLK48M
I
USB 48 MHz clock input:
3.3V/5V -M
This signal provides the fundamental clock for the USB
Controller.
OC[0:5]#
I/O
USB Por t 0-5 Over cur r ent Detection:
3.3V/5V - AUX
OC[0:5]# are used to detect the overcurrent condition of USB
Ports 0-5.
UV[2:0]+,
I/O
USB Por t [2:0] Differ ential:
UV[2:0]-
3.3V - AUX
These differential pairs are used to transmit Data/Address
/Command signals for ports 0-2. (USB controller 1)
UV[5:3]+,
I/O
USB Por t [5:3] Differ ential:
UV[5:3]-
3.3V - AUX
These differential pairs are used to transmit Data/Address/
Command signals for ports 3-5. (USB controller 2)
Signal Descr iption
Signal Descr iption
LPC Inter face
Name
Pin Attr
LAD[3:0]
I/O
LPC Addr ess/Data Bus:
3.3V/5V-M
LPC controller drives these four pins to transmit LPC command,
address, and data to LPC device.
LDRQ#
I
LPC DMA Request 0:
3.3V/5V-M
This pin is used by LPC device to request DMA cycle.
LDRQ1# /
I
LPC DMA Request 1:
GPIO1
I/O
This pin is used by LPC device to request DMA cycle.
3.3V/5V-M
LFRAME#
O
LPC Fr ame:
3.3V -M
This pin is used to notify LPC device that a start or a abort LPC
cycle will occur.
SIRQ
I/O
I/O
3.3V/5V -M
3.3V/5V -M
TRC Inter face
Name
Pin Attr
BATOK
I
Batter y Power OK:
3.3V -RTC
When the internal RTC is enabled, this signal is used to indicate
that the power of RTC well is stable. It is also used to reset the
logic in RTC well. If the internal RTC is disabled, this pin
should be tied low.
OSC32KHI
I
RTC 32.768 KHz Input:
3.3V-RTC
When internal RTC is enabled, this pin provides the 32.768
KHz clock signal from external crystal or oscillator.
OSC32KHO
O
RTC 32.768 KHz Output:
<3.3V -RTC
When internal RTC is enabled, this pin should be connected
with the other end of the 32.768 KHz crystal or left unconnected
if an external oscillator is used.
PWROK
I
Main Power OK:
3.3V-RTC
A high-level input to this signal indicates the power being
supplied to the system is in stable operating state. During the
period of PWROK being low, PCIRST# will all be asserted
until after PWROK goes high for 12 ms.
87
Technical Service Manual
Signal Descr iption
Signal Descr iption
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