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LiAM User's Manual
Note: The absolute maximum current that can be sunk/sourced by the output
status relays (solid state relay pins 5 and 6) is 100mA.
Interlock 1 (the displayed interlock name shown on the front display can be
changed with the user requirements, see 'MWF command' and Memory mapping
sections for further details) is hardware-activated when at least high-level LVTTL
3.3V are applied between pin 2 and return pin 1.
Suggested cable section for interlocks and output status connections is 0.25
2
mm
(i.e. 23 AWG).
3.1.2.1 Interlocks Enabling/Disabling
Each LiAM external interlock can be enabled and disabled by writing to the
interlock enable mask to the EEPROM cell 48. A value of '1' means that the interlock
is enabled while a '0' value that the corresponding interlock is disabled.
The value to be written is the ASCII character, formed by a single hexadecimal
digit, which corresponds to the binary enabling/disabling mask; the two external
interlocks are numbered from #1 and #2.
Example: if only interlock #2 has to be enabled, the following command needs
to be sent to the power supply:
The sent string has to be so interpreted:
0
don't care
In order to make this command taking effect it is necessary to perform a
'MUP\r' (Module Update Parameters) command – see "MUP command" section for
further details.
The MRG:48\r command returns a string containing the ASCII correspondent of
the interlock enable mask and contains information about what interlocks are enabled
and what are disabled.
3.1.2.2 Interlocks Activation States
Each LiAM external interlock can be chosen to trip at a HIGH or a LOW logic
level. A value of '1' means that the interlock trips when the input signal to the
corresponding interlock is shorted and a '0' that the corresponding interlock trips
when the input is open.
33
MWG:48:2\r
2
0
Interlock 2
don't care
Enabled
LiAM Description
1
0
Interlock 1
Disabled
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