Table 24. 3Dnow! Extensions - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization
Table 23. 3DNow!™ Instructions (Continued)
Instruction Mnemonic
PFRSQRT mmreg, mem64
PFSUB mmreg1, mmreg2
PFSUB mmreg, mem64
PFSUBR mmreg1, mmreg2
PFSUBR mmreg, mem64
PI2FD mmreg1, mmreg2
PI2FD mmreg, mem64
PMULHRW mmreg1, mmreg2 0Fh, 0Fh
PMULHRW mmreg1, mem64
PREFETCH mem8
PREFETCHW mem8
Notes:
1. For the PREFETCH and PREFETCHW instructions, the mem8 value refers to an address in the 64-byte line that will be
prefetched.
2. The byte listed in the column titled 'imm8' is actually the opcode byte.
Table 24. 3DNow!™ Extensions
Instruction Mnemonic
PF2IW mmreg1, mmreg2
PF2IW mmreg, mem64
PFNACC mmreg1, mmreg2
PFNACC mmreg, mem64
PFPNACC mmreg1, mmreg2
PFPNACC mmreg, mem64
PI2FW mmreg1, mmreg2
PI2FW mmreg, mem64
PSWAPD mmreg1, mmreg2
PSWAPD mmreg, mem64
218
Prefix ModR/M
imm8
Byte(s) Byte
0Fh, 0Fh 97h mm-xxx-xxx DirectPath
0Fh, 0Fh 9Ah 11-xxx-xxx
0Fh, 0Fh 9Ah mm-xxx-xxx DirectPath
0Fh, 0Fh AAh 11-xxx-xxx
0Fh, 0Fh AAh mm-xxx-xxx DirectPath
0Fh, 0Fh 0Dh 11-xxx-xxx
0Fh, 0Fh 0Dh mm-xxx-xxx DirectPath
B7h 11-xxx-xxx
0Fh, 0Fh B7h mm-xxx-xxx DirectPath
0Fh 0Dh mm-000-xxx DirectPath
0Fh 0Dh mm-001-xxx DirectPath
Prefix ModR/M
imm8
Byte(s) Byte
0Fh, 0Fh 1Ch 11-xxx-xxx
0Fh, 0Fh 1Ch mm-xxx-xxx DirectPath
0Fh, 0Fh 8Ah 11-xxx-xxx
0Fh, 0Fh 8Ah mm-xxx-xxx DirectPath
0Fh, 0Fh 8Eh 11-xxx-xxx
0Fh, 0Fh 8Eh mm-xxx-xxx DirectPath
0Fh, 0Fh 0Ch 11-xxx-xxx
0Fh, 0Fh 0Ch mm-xxx-xxx DirectPath
0Fh, 0Fh BBh 11-xxx-xxx
0Fh, 0Fh BBh mm-xxx-xxx DirectPath
Decode FPU
Type Pipe(s)
FMUL
DirectPath FADD
FADD
DirectPath FADD
FADD
DirectPath FADD
FADD
DirectPath FMUL
FMUL
-
-
Decode FPU
Type Pipe(s)
DirectPath FADD
FADD
DirectPath FADD
FADD
DirectPath FADD
FADD
DirectPath FADD
FADD
DirectPath FADD/FMUL
FADD/FMUL
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Note
1, 2
1, 2
Note