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22007E/0—November 1999
AMD Athlon™ Processor Family
AMD Athlon™ Processor Family
Appendix B: Pipeline and Execution Unit Resources Overview. Describes
in detail the execution units and its relation to the instruction
pipeline.
Appendix C: Implementation of Write Combining. D e s c r i b e s
algorithm used by the AMD Athlon processor to write combine.
Appendix D: Performance Monitoring Counters. Describes the usage of
the performance counters available in the AMD Athlon
processor.
Appendix E: Programming the MTRR and PAT. D e s c r i b e s t h e s t e p s
needed to program the Memory Type Range Registers and the
Page Attribute Table.
Appendix F: Instruction Dispatch and Execution Resources. L i s t s
instruction's execution resource usage.
Appendix G: DirectPath versus VectorPath Instructions. L i s t s t h e x 8 6
instructions that are DirectPath and VectorPath instructions.
The AMD Athlon processor family uses state-of-the-art
decoupled decode/execution design techniques to deliver
next-generation performance with x86 binary software
compatibility. This next-generation processor family advances
x86 code execution by using flexible instruction predecoding,
wide and balanced decoders, aggressive out-of-order execution,
parallel integer execution pipelines, parallel floating-point
execution pipelines, deep pipelined execution for higher
delivered operating frequency, dedicated backside cache
memory, and a new high-performance double-rate 64-bit local
bus. As an x86 binary-compatible processor, the AMD Athlon
processor implements the industry-standard x86 instruction set
by decoding and executing the x86 instructions using a
proprietary microarchitecture. This microarchitecture allows
the delivery of maximum performance when running x86-based
PC software.
AMD Athlon™ Processor x86 Code Optimization
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