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22007E/0—November 1999
Pipelined Pair of 24-Bit Precision Divides
Newton-Raphson Reciprocal
Use 3DNow!™ Instructions for Fast Division
This divide operation executes with a total latency of 21 cycles,
assuming that the program hides the latency of the first
MOVD/MOVQ instructions within preceding code.
Example:
MOVQ
MM0, [DIVISORS]
PFRCP
MM1, MM0
MOVQ
MM2, MM0
PUNPCKHDQ
MM0, MM0
PFRCP
MM0, MM0
PUNPCKLDQ
MM1, MM0
MOVQ
MM0, [DIVIDENDS]
PFRCPIT1
MM2, MM1
PFRCPIT2
MM2, MM1
PFMUL
MM0, MM2
Consider the quotient q =
lookup can be used to quickly produce a 14-to-15-bit precision
1
approximation of
24-bit precision reciprocal can then be quickly computed from
this approximation using a Newton Raphson algorithm.
The general Newton-Raphson recurrence for the reciprocal is as
follows:
•
Z
= Z
(2 – b
i+1
i
Given that the initial approximation is accurate to at least 14
bits, and that a full IEEE single-precision mantissa contains 24
bits, just one Newton-Raphson iteration is required. The
following sequence shows the 3DNow! instructions that produce
the initial reciprocal approximation, compute the full precision
reciprocal from the approximation, and finally, complete the
a
desired divide of
/
X
= PFRCP(b)
0
X
= PFRCPIT1(b,X
1
0
X
= PFRCPIT2(X
,X
2
1
q
= PFMUL(a,X
)
2
The 24-bit final reciprocal value is X
processor 3DNow! technology implementation the operand X
contains the correct round-to-nearest single precision
reciprocal for approximately 99% of all arguments.
AMD Athlon™ Processor x86 Code Optimization
;
y | x
; 1/x | 1/x
;
y | x
;
y | y
; 1/y | 1/y
; 1/y | 1/x
;
z | w
; 1/y | 1/x
; 1/y | 1/x
; z/y | w/x
a
/
. An (on-chip) ROM-based table
b
using just one PFRCP instruction. A full
/
b
•
Z
)
i
.
b
)
)
0
(approximate)
(approximate)
(approximate)
(intermediate)
(final)
. In the AMD Athlon
2
2
109
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