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AMD Athlon™ Processor x86 Code Optimization
Table 13. Standard MTRR Types and Properties
Memory Type
Uncacheable (UC)
Write Combining (WC)
Reserved
Reserved
Writethrough (WT)
Write Protected (WP)
Writeback (WB)
Reserved
MTRR Overlapping
176
Encoding in
Internally
MTRR
Cacheable
0
No
1
No
2
-
3
-
4
Yes
Yes, reads
5
No, Writes
6
Yes
7-255
-
Note that if two or more variable memory ranges match then
the interactions are defined as follows:
1. If the memory types are identical, then that memory type is
used.
2. If one or more of the memory types is UC, the UC memory
type is used.
3. If one or more of the memory types is WT and the only other
matching memory type is WB then the WT memory type is
used.
4. Otherwise, if the combination of memory types is not listed
above then the behavior of the processor is undefined.
The Intel documentation (P6/PII) states that the mapping of
large pages into regions that are mapped with differing memory
types can result in undefined behavior. However, testing shows
that these processors decompose these large pages into 4-Kbyte
pages.
When a large page (2 Mbytes/4 Mbytes) mapping covers a
region that contains more than one memory type (as mapped by
the MTRRs), the AMD Athlon processor does not suppress the
caching of that large page mapping and only caches the
mapping for just that 4-Kbyte piece in the 4-Kbyte TLB.
Therefore, the AMD Athlon processor does not decompose
large pages under these conditions. The fixed range MTRRs are
Allows
Writeback
Speculative
Cacheable
Reads
No
No
No
Yes
-
-
-
-
No
Yes
No
Yes
Yes
Yes
-
-
Memory Type Range Register (MTRR) Mechanism
22007E/0—November 1999
Memory Ordering Model
Strong ordering
Weak ordering
-
-
Speculative ordering
Speculative ordering
Speculative ordering
-
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