Integer Pipeline Stages; Figure 7. Integer Execution Pipeline; Figure 8. Integer Pipeline Stages - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization

Integer Pipeline Stages

Instruction Control Unit and Register Files
IEU0 AGU0
IEU0 AGU0
Integer Multiply (IMUL)
Integer Multiply (IMUL)

Figure 7. Integer Execution Pipeline

7
S C H E D

Figure 8. Integer Pipeline Stages

144
operands mapped to registers. Both integer and floating-point
MacroOPs are placed into the ICU.
The integer execution pipeline consists of four or more stages
for scheduling and execution and, if necessary, accessing data
in the processor caches or system memory. There are three
integer pipes associated with the three IEUs.
M acroOPs
Integer Scheduler
(18-entry)
IEU1
IEU1
Figure 7 and Figure 8 show the integer execution resources and
the pipeline stages, which are described in the following
sections.
8
E X E C
M acroOPs
AGU1 IEU2
AGU1 IEU2
9
1 0
A D D G E N D C A C C
22007E/0—November 1999
Pipeline
Pipeline
Stage Stage
7 7
8
8
AGU2
AGU2
11
R E S P
Integer Pipeline Stages