AMD Athlon Processor x86 Optimization Manual page 231

22007E/0—November 1999
Table 22. Floating-Point Instructions (Continued)
Instruction Mnemonic
FLDCW [mem16]
FLDENV [mem14byte]
FLDENV [mem28byte]
FLDL2E
FLDL2T
FLDLG2
FLDLN2
FLDPI
FLDZ
FMUL ST, ST(i)
FMUL ST(i), ST
FMUL [mem32real]
FMUL [mem64real]
FMULP ST, ST(i)
FNOP
FPTAN
FPATAN
FPREM
FPREM1
FRNDINT
FRSTOR [mem94byte]
FRSTOR [mem108byte]
FSAVE [mem94byte]
FSAVE [mem108byte]
FSCALE
FSIN
FSINCOS
FSQRT
FST [mem32real]
FST [mem64real]
FST ST(i)
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
Instruction Dispatch and Execution Resources
First Second ModR/M
Byte Byte Byte
D9h mm-101-xxx VectorPath
D9h mm-100-xxx VectorPath
D9h mm-100-xxx VectorPath
D9h EAh
D9h E9h
D9h ECh
D9h EDh
D9h EBh
D9h EEh
D8h 11-001-xxx
DCh 11-001-xxx
D8h mm-001-xxx DirectPath
DCh mm-001-xxx DirectPath
DEh 11-001-xxx
D9h D0h
D9h F2h
D9h F3h
D9h F8h
D9h F5h
D9h FCh
DDh mm-100-xxx VectorPath
DDh mm-100-xxx VectorPath
DDh mm-110-xxx VectorPath
DDh mm-110-xxx VectorPath
D9h FDh
D9h FEh
D9h FBh
D9h FAh
D9h mm-010-xxx DirectPath
DDh mm-010-xxx DirectPath
DDh 11-010xxx
AMD Athlon™ Processor x86 Code Optimization
Decode FPU
Type Pipe(s)
DirectPath FSTORE
DirectPath FSTORE
DirectPath FSTORE
DirectPath FSTORE
DirectPath FSTORE
DirectPath FSTORE
DirectPath FMUL
DirectPath FMUL
FMUL
FMUL
DirectPath FMUL
DirectPath FADD/FMUL/FSTORE
VectorPath
VectorPath
DirectPath FMUL
DirectPath FMUL
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath FMUL
FSTORE
FSTORE
DirectPath FADD/FMUL
Note
1
1
1
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