AMD Athlon Processor x86 Optimization Manual page 214

AMD Athlon™ Processor x86 Code Optimization
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
MOV EDX, imm16/32
MOV EBX, imm16/32
MOV ESP, imm16/32
MOV EBP, imm16/32
MOV ESI, imm16/32
MOV EDI, imm16/32
MOV mreg8, imm8
MOV mem8, imm8
MOV mreg16/32, imm16/32
MOV mem16/32, imm16/32
MOVSB mem8,mem8
MOVSD mem16, mem16
MOVSW mem32, mem32
MOVSX reg16/32, mreg8
MOVSX reg16/32, mem8
MOVSX reg32, mreg16
MOVSX reg32, mem16
MOVZX reg16/32, mreg8
MOVZX reg16/32, mem8
MOVZX reg32, mreg16
MOVZX reg32, mem16
MUL AL, mreg8
MUL AL, mem8
MUL AX, mreg16
MUL AX, mem16
MUL EAX, mreg32
MUL EAX, mem32
NEG mreg8
NEG mem8
NEG mreg16/32
NEG mem16/32
NOP (XCHG EAX, EAX)
NOT mreg8
198
First Second ModR/M
Byte Byte Byte
BAh
BBh
BCh
BDh
BEh
BFh
C6h 11-000-xxx
C6h mm-000-xxx DirectPath
C7h 11-000-xxx
C7h mm-000-xxx DirectPath
A4h
A5h
A5h
0Fh BEh 11-xxx-xxx
0Fh BEh mm-xxx-xxx DirectPath
0Fh BFh 11-xxx-xxx
0Fh BFh mm-xxx-xxx DirectPath
0Fh B6h 11-xxx-xxx
0Fh B6h mm-xxx-xxx DirectPath
0Fh B7h 11-xxx-xxx
0Fh B7h mm-xxx-xxx DirectPath
F6h 11-100-xxx
F6h mm-100-xx VectorPath
F7h 11-100-xxx
F7h mm-100-xxx VectorPath
F7h 11-100-xxx
F7h mm-100-xx VectorPath
F6h 11-011-xxx
F6h mm-011-xx
F7h 11-011-xxx
F7h mm-011-xx
90h
F6h 11-010-xxx
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Decode
Type
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath