AMD Athlon Processor x86 Optimization Manual page 206

AMD Athlon™ Processor x86 Code Optimization
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
AND mem8, reg8
AND mreg16/32, reg16/32
AND mem16/32, reg16/32
AND reg8, mreg8
AND reg8, mem8
AND reg16/32, mreg16/32
AND reg16/32, mem16/32
AND AL, imm8
AND EAX, imm16/32
AND mreg8, imm8
AND mem8, imm8
AND mreg16/32, imm16/32
AND mem16/32, imm16/32
AND mreg16/32, imm8 (sign extended)
AND mem16/32, imm8 (sign extended)
ARPL mreg16, reg16
ARPL mem16, reg16
BOUND
BSF reg16/32, mreg16/32
BSF reg16/32, mem16/32
BSR reg16/32, mreg16/32
BSR reg16/32, mem16/32
BSWAP EAX
BSWAP ECX
BSWAP EDX
BSWAP EBX
BSWAP ESP
BSWAP EBP
BSWAP ESI
BSWAP EDI
BT mreg16/32, reg16/32
BT mem16/32, reg16/32
BT mreg16/32, imm8
190
First Second ModR/M
Byte Byte Byte
20h mm-xxx-xxx DirectPath
21h 11-xxx-xxx
21h mm-xxx-xxx DirectPath
22h 11-xxx-xxx
22h mm-xxx-xxx DirectPath
23h 11-xxx-xxx
23h mm-xxx-xxx DirectPath
24h
25h
80h 11-100-xxx
80h mm-100-xxx DirectPath
81h 11-100-xxx
81h mm-100-xxx DirectPath
83h 11-100-xxx
83h mm-100-xxx DirectPath
63h 11-xxx-xxx
63h mm-xxx-xxx VectorPath
62h
0Fh BCh 11-xxx-xxx
0Fh BCh mm-xxx-xxx VectorPath
0Fh BDh 11-xxx-xxx
0Fh BDh mm-xxx-xxx VectorPath
0Fh C8h
0Fh C9h
0Fh CAh
0Fh CBh
0Fh CCh
0Fh CDh
0Fh CEh
0Fh CFh
0Fh A3h 11-xxx-xxx
0Fh A3h mm-xxx-xxx VectorPath
0Fh BAh 11-100-xxx
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Decode
Type
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath