Table 20. Mmx™ Instructions - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization
Table 20. MMX™ Instructions
Instruction Mnemonic
EMMS
MOVD mmreg, reg32
MOVD mmreg, mem32
MOVD reg32, mmreg
MOVD mem32, mmreg
MOVQ mmreg1, mmreg2
MOVQ mmreg, mem64
MOVQ mmreg2, mmreg1
MOVQ mem64, mmreg
PACKSSDW mmreg1, mmreg2
PACKSSDW mmreg, mem64
PACKSSWB mmreg1, mmreg2
PACKSSWB mmreg, mem64
PACKUSWB mmreg1, mmreg2
PACKUSWB mmreg, mem64
PADDB mmreg1, mmreg2
PADDB mmreg, mem64
PADDD mmreg1, mmreg2
PADDD mmreg, mem64
PADDSB mmreg1, mmreg2
PADDSB mmreg, mem64
PADDSW mmreg1, mmreg2
PADDSW mmreg, mem64
PADDUSB mmreg1, mmreg2
PADDUSB mmreg, mem64
PADDUSW mmreg1, mmreg2
PADDUSW mmreg, mem64
PADDW mmreg1, mmreg2
PADDW mmreg, mem64
PAND mmreg1, mmreg2
PAND mmreg, mem64
Notes:
1. Bits 2, 1, and 0 of the modR/M byte select the integer register.
208
Prefix First ModR/M
Byte(s) Byte Byte
0Fh 77h
0Fh 6Eh 11-xxx-xxx
0Fh 6Eh mm-xxx-xxx DirectPath
0Fh 7Eh 11-xxx-xxx
0Fh 7Eh mm-xxx-xxx DirectPath
0Fh 6Fh 11-xxx-xxx
0Fh 6Fh mm-xxx-xxx DirectPath
0Fh 7Fh 11-xxx-xxx
0Fh 7Fh mm-xxx-xxx DirectPath
0Fh 6Bh 11-xxx-xxx
0Fh 6Bh mm-xxx-xxx DirectPath
0Fh 63h 11-xxx-xxx
0Fh 63h mm-xxx-xxx DirectPath
0Fh 67h 11-xxx-xxx
0Fh 67h mm-xxx-xxx DirectPath
0Fh FCh 11-xxx-xxx
0Fh FCh mm-xxx-xxx DirectPath
0Fh FEh 11-xxx-xxx
0Fh FEh mm-xxx-xxx DirectPath
0Fh ECh 11-xxx-xxx
0Fh ECh mm-xxx-xxx DirectPath
0Fh EDh 11-xxx-xxx
0Fh EDh mm-xxx-xxx DirectPath
0Fh DCh 11-xxx-xxx
0Fh DCh mm-xxx-xxx DirectPath
0Fh DDh 11-xxx-xxx
0Fh DDh mm-xxx-xxx DirectPath
0Fh FDh 11-xxx-xxx
0Fh FDh mm-xxx-xxx DirectPath
0Fh DBh 11-xxx-xxx
0Fh DBh mm-xxx-xxx DirectPath
Decode
FPU Pipe(s)
Type
DirectPath FADD/FMUL/FSTORE
VectorPath
FADD/FMUL/FSTORE
VectorPath
FSTORE
DirectPath FADD/FMUL
FADD/FMUL/FSTORE
DirectPath FADD/FMUL
FSTORE
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Notes
1
1