AMD Athlon Processor x86 Optimization Manual page 221

22007E/0—November 1999
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
SHR mem16/32, imm8
SHR mreg8, 1
SHR mem8, 1
SHR mreg16/32, 1
SHR mem16/32, 1
SHR mreg8, CL
SHR mem8, CL
SHR mreg16/32, CL
SHR mem16/32, CL
SHLD mreg16/32, reg16/32, imm8
SHLD mem16/32, reg16/32, imm8
SHLD mreg16/32, reg16/32, CL
SHLD mem16/32, reg16/32, CL
SHRD mreg16/32, reg16/32, imm8
SHRD mem16/32, reg16/32, imm8
SHRD mreg16/32, reg16/32, CL
SHRD mem16/32, reg16/32, CL
SLDT mreg16
SLDT mem16
SMSW mreg16
SMSW mem16
STC
STD
STI
STOSB mem8, AL
STOSW mem16, AX
STOSD mem32, EAX
STR mreg16
STR mem16
SUB mreg8, reg8
SUB mem8, reg8
SUB mreg16/32, reg16/32
SUB mem16/32, reg16/32
Instruction Dispatch and Execution Resources
AMD Athlon™ Processor x86 Code Optimization
First Second ModR/M
Byte Byte Byte
C1h mm-101-xxx DirectPath
D0h 11-101-xxx
D0h mm-101-xxx DirectPath
D1h 11-101-xxx
D1h mm-101-xxx DirectPath
D2h 11-101-xxx
D2h mm-101-xxx DirectPath
D3h 11-101-xxx
D3h mm-101-xxx DirectPath
0Fh A4h 11-xxx-xxx
0Fh A4h mm-xxx-xxx VectorPath
0Fh A5h 11-xxx-xxx
0Fh A5h mm-xxx-xxx VectorPath
0Fh ACh 11-xxx-xxx
0Fh ACh mm-xxx-xxx VectorPath
0Fh ADh 11-xxx-xxx
0Fh ADh mm-xxx-xxx VectorPath
0Fh 00h 11-000-xxx
0Fh 00h mm-000-xxx VectorPath
0Fh 01h 11-100-xxx
0Fh 01h mm-100-xxx VectorPath
F9h
FDh
FBh
AAh
ABh
ABh
0Fh 00h 11-001-xxx
0Fh 00h mm-001-xxx VectorPath
28h 11-xxx-xxx
28h mm-xxx-xxx DirectPath
29h 11-xxx-xxx
29h mm-xxx-xxx DirectPath
Decode
Type
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
205