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AMD Athlon™ Processor x86 Code Optimization
MTRR Fixed-Range
Register Format
Table 17. MTRR Fixed Range Register Format
63:56
55:48
47:40
70000-
60000-
50000-
7FFFF
6FFFF
5FFFF
9C000
98000
94000
9FFFF
9BFFF
97FFF
BC000-
B8000-
B4000-
BFFFF
BBFFF
B7FFF
C7000-
C6000-
C5000-
C7FFF
C6FFF
C5FFF
CF000C-
CE000-
CD000-
FFFF
CEFFF
CDFFF
D7000-
D6000-
D5000-
D7FFF
D6FFF
D5FFF
DF000-
DE000-
DD000-
DFFFF
DEFFF
DDFFF
E7000-
E6000-
E5000-
E7FFF
E6FFF
E5FFF
EF000-
EE000-
ED000-
EFFFF
EEFFF
EDFFF
F7000
F6000
F5000
F7FFF
F6FFF
F5FFF
FF000
FE000
FD000-
FDFFF
FFFFF
FEFFF
182
The memory types defined for memory segments defined in
each of the MTRR fixed-range registers are defined in Table 17
(Also See "Standard MTRR Types and Propert ies" on
page 176.).
Address Range (in hexadecimal)
39:32
31:24
40000-
30000-
4FFFF
3FFFF
90000
8C000
93FFF
8FFFF
B0000-
AC000-
B3FFF
AFFFF
C4000-
C3000-
C4FFF
C3FFF
CC000-
CB000-
CCFFF
CBFFF
D4000-
D3000-
D4FFF
D3FFF
DC000-
DB000-
DCFFF
DBFFF
E4000-
E3000-
E4FFF
E3FFF
EC000-
EB000-
ECFFF
EBFFF
F4000
F3000
F4FFF
F3FFF
FC000-
FB000-
FCFFF
FBFFF
23:16
15:8
7:0
20000-
10000-
00000-
2FFFF
1FFFF
0FFFF
88000
84000
80000
8BFFF
87FFF
83FFF
A8000-
A4000-
A0000-
ABFFF
A7FFF
A3FFF
C2000-
C1000-
C0000-
C2FFF
C1FFF
C0FFF
CA000-
C9000-
C8000-
CAFFF
C9FFF
C8FFF
D2000-
D1000-
D0000-
D2FFF
D1FFF
D0FFF
DA000-
D9000-
D8000-
DAFFF
D9FFF
D8FFF
E2000-
E1000-
E0000-
E2FFF
E1FFF
E0FFF
EA000-
E9000-
E8000-
EAFFF
E9FFF
E8FFF
F2000
F1000
F0000
F2FFF
F1FFF
F0FFF
F9000
F8000
FA000-
FAFFF
F9FFF
F8FFF
22007E/0—November 1999
Register
MTRR_fix64K_00000
MTRR_fix16K_80000
MTRR_fix16K_A0000
MTRR_fix4K_C0000
MTRR_fix4K_C8000
MTRR_fix4K_D0000
MTRR_fix4K_D8000
MTRR_fix4K_E0000
MTRR_fix4K_E8000
MTRR_fix4K_F0000
MTRR_fix4K_F8000
Page Attribute Table (PAT)
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