AMD Athlon Processor x86 Optimization Manual page 69

22007E/0—November 1999
Misaligned
Store-Buffer Data
Forwarding
Restriction
High-Byte
Store-Buffer Data
Forwarding
Restriction
Store-to-Load Forwarding Restrictions
Example 5 (Preferred):
MOVD [foo], MM1
PUNPCKHDQ MM1, MM1
MOVD [foo+4], MM1
...
ADD EAX, [foo]
ADD EDX, [foo+4]
If the following condition is present, there is a misaligned
store-buffer data forwarding restriction:
The store or load address is misaligned. For example, a
quadword store is not aligned to a quadword boundary, a
doubleword store is not aligned to doubleword boundary,
etc.
A common case of misaligned store-data forwarding involves
the passing of misaligned quadword floating-point data on the
doubleword-aligned integer stack. Avoid the type of code shown
in the following example.
Example 6 (Avoid):
MOV ESP, 24h
FSTP QWORD PTR [ESP] ;esp=24
.
.
.
FLD QWORD PTR[ESP]
If the following condition is present, there is a high-byte
store-data buffer forwarding restriction:
The store data is from a high-byte register (AH, BH, CH,
DH).
Avoid the type of code shown in the following example.
Example 7 (Avoid):
MOV EAX, 10h
MOV [EAX], BH
.
MOV DL, [EAX]
AMD Athlon™ Processor x86 Code Optimization
;store lower half
;get upper half into lower half
;store lower half
;fine
;fine
;store occurs to quadword
; misaligned address
;quadword load cannot forward
; from quadword misaligned
; 'fstp[esp]' store OP
;high-byte store
;load cannot forward from
; high-byte store
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