AMD Athlon Processor x86 Optimization Manual page 210

AMD Athlon™ Processor x86 Code Optimization
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
DIV EAX, mreg16/32
DIV EAX, mem16/32
ENTER
IDIV mreg8
IDIV mem8
IDIV EAX, mreg16/32
IDIV EAX, mem16/32
IMUL reg16/32, imm16/32
IMUL reg16/32, mreg16/32, imm16/32
IMUL reg16/32, mem16/32, imm16/32
IMUL reg16/32, imm8 (sign extended)
IMUL reg16/32, mreg16/32, imm8 (signed)
IMUL reg16/32, mem16/32, imm8 (signed)
IMUL AX, AL, mreg8
IMUL AX, AL, mem8
IMUL EDX:EAX, EAX, mreg16/32
IMUL EDX:EAX, EAX, mem16/32
IMUL reg16/32, mreg16/32
IMUL reg16/32, mem16/32
IN AL, imm8
IN AX, imm8
IN EAX, imm8
IN AL, DX
IN AX, DX
IN EAX, DX
INC EAX
INC ECX
INC EDX
INC EBX
INC ESP
INC EBP
INC ESI
INC EDI
194
First Second ModR/M
Byte Byte Byte
F7h 11-110-xxx
F7h mm-110-xxx VectorPath
C8
F6h 11-111-xxx
F6h mm-111-xxx VectorPath
F7h 11-111-xxx
F7h mm-111-xxx VectorPath
69h 11-xxx-xxx
69h 11-xxx-xxx
69h mm-xxx-xxx VectorPath
6Bh 11-xxx-xxx
6Bh 11-xxx-xxx
6Bh mm-xxx-xxx VectorPath
F6h 11-101-xxx
F6h mm-101-xxx VectorPath
F7h 11-101-xxx
F7h mm-101-xxx VectorPath
0Fh AFh 11-xxx-xxx
0Fh AFh mm-xxx-xxx VectorPath
E4h
E5h
E5h
ECh
EDh
EDh
40h
41h
42h
43h
44h
45h
46h
47h
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Decode
Type
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath