Integer Pipeline Operations; Table 2. Integer Pipeline Operation Types; Table 3. Integer Decode Types - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999

Integer Pipeline Operations

Execution Unit Resources
Table 2 shows the category or type of operations handled by the
integer pipeline. Table 3 shows examples of the decode type.
Table 2. Integer Pipeline Operation Types
Category
Integer Memory Load or Store Operations
Address Generation Operations
Integer Execution Unit Operations
Integer Multiply Operations
Table 3. Integer Decode Types
x86 Instruction Decode Type
MOV CX, [SP+4] DirectPath
ADD AX, BX DirectPath
CMP CX, [AX] VectorPath
JZ Addr DirectPath
As shown in Table 2, the MOV instruction early decodes in the
DirectPath decoder and requires two OPs—an address
generation operation for the indirect address and a data load
from memory into a register. The ADD instruction early
decodes in the DirectPath decoder and requires a single OP
that can be executed in one of the three IEUs. The CMP
instruction early decodes in the VectorPath and requires three
OPs—an address generation operation for the indirect address,
a data load from memory, and a compare to CX using an IEU.
The final JZ instruction is a simple operation that early decodes
in the DirectPath decoder and requires a single OP. Not shown
is a load-op-store instruction, which translates into only one
MacroOP (one AGU OP, one IEU OP, and one L/S OP).
AMD Athlon™ Processor x86 Code Optimization
Execution Unit
L/S
AGU
IEU
IMUL
OPs
AGU, L/S
IEU
AGU, L/S, IEU
IEU
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