AMD Athlon Processor x86 Optimization Manual page 222

AMD Athlon™ Processor x86 Code Optimization
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
SUB reg8, mreg8
SUB reg8, mem8
SUB reg16/32, mreg16/32
SUB reg16/32, mem16/32
SUB AL, imm8
SUB EAX, imm16/32
SUB mreg8, imm8
SUB mem8, imm8
SUB mreg16/32, imm16/32
SUB mem16/32, imm16/32
SUB mreg16/32, imm8 (sign extended)
SUB mem16/32, imm8 (sign extended)
SYSCALL
SYSENTER
SYSEXIT
SYSRET
TEST mreg8, reg8
TEST mem8, reg8
TEST mreg16/32, reg16/32
TEST mem16/32, reg16/32
TEST AL, imm8
TEST EAX, imm16/32
TEST mreg8, imm8
TEST mem8, imm8
TEST mreg8, imm16/32
TEST mem8, imm16/32
VERR mreg16
VERR mem16
VERW mreg16
VERW mem16
WAIT
WBINVD
WRMSR
206
First Second ModR/M
Byte Byte Byte
2Ah 11-xxx-xxx
2Ah mm-xxx-xxx DirectPath
2Bh 11-xxx-xxx
2Bh mm-xxx-xxx DirectPath
2Ch
2Dh
80h 11-101-xxx
80h mm-101-xxx DirectPath
81h 11-101-xxx
81h mm-101-xxx DirectPath
83h 11-101-xxx
83h mm-101-xxx DirectPath
0Fh 05h
0Fh 34h
0Fh 35h
0Fh 07h
84h 11-xxx-xxx
84h mm-xxx-xxx DirectPath
85h 11-xxx-xxx
85h mm-xxx-xxx DirectPath
A8h
A9h
F6h 11-000-xxx
F6h mm-000-xxx DirectPath
F7h 11-000-xxx
F7h mm-000-xxx DirectPath
0Fh 00h 11-100-xxx
0Fh 00h mm-100-xxx VectorPath
0Fh 00h 11-101-xxx
0Fh 00h mm-101-xxx VectorPath
9Bh
0Fh 09h
0Fh 30h
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Decode
Type
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
DirectPath
VectorPath
VectorPath