Integer Scheduler; Integer Execution Unit; Figure 2. Integer Execution Pipeline - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999

Integer Scheduler

Integer Execution Unit

In s t r u c t io n C o n t r o l U n it a n d R e g is t e r F ile s
M a c r o O P s
IE U 0 A G U 0
IE U 0 A G U 0
In te g e r M u lt ip ly ( IM U L )
In te g e r M u lt ip ly ( IM U L )

Figure 2. Integer Execution Pipeline

AMD Athlon™ Processor Microarchitecture
The integer scheduler is based on a three-wide queuing system
(also known as a reservation station) that feeds three integer
execution positions or pipes. The reservation stations are six
entries deep, for a total queuing system of 18 integer
MacroOPs.Each reservation station divides the MacroOPs into
integer and address generation OPs, as required.
The integer execution pipeline consists of three identical
pipes — 0, 1, and 2. Each integer pipe consists of an integer
execution unit (IEU) and an address generation unit (AGU).
The integer execution pipeline is organized to match the three
MacroOP dispatch pipes in the ICU as shown in Figure 2 on
page 135. MacroOPs are broken down into OPs in the
schedulers. OPs issue when their operands are available either
from the register file or result buses.
OPs are executed when their operands are available. OPs from
a single MacroOP can execute out-of-order. In addition, a
particular integer pipe can be executing two OPs from different
MacroOPs (one in the IEU and one in the AGU) at the same
time.
In t e g e r S c h e d u le r
( 1 8 - e n t r y )
IE U 1 A G U 1
IE U 1 A G U 1
AMD Athlon™ Processor x86 Code Optimization
M a c r o O P s
IE U 2
IE U 2
P ip e lin e
P ip e lin e
S t a g e S ta g e
7
7
8
8
A G U 2
A G U 2
135