AMD Athlon Processor x86 Optimization Manual page 161

22007E/0—November 1999
Cycle 7–SCHED
Cycle 8–EXEC
Cycle 9–ADDGEN
Cycle 10–DCACC
Cycle 11–RESP
Integer Pipeline Stages
In the scheduler (SCHED) pipeline stage, the scheduler buffers
can contain MacroOPs that are waiting for integer operands
from the ICU or the IEU result bus. When all operands are
received, SCHED schedules the MacroOP for execution and
issues the OPs to the next stage, EXEC.
In the execution (EXEC) pipeline stage, the OP and its
associated operands are processed by an integer pipe (either
the IEU or the AGU). If addresses must be calculated to access
data necessary to complete the operation, the OP proceeds to
the next stages, ADDGEN and DCACC.
In the address generation (ADDGEN) pipeline stage, the load
or store OP calculates a linear address, which is sent to the data
cache TLBs and caches.
In the data cache access (DCACC) pipeline stage, the address
generated in the previous pipeline stage is used to access the
data cache arrays and TLBs. Any OP waiting in the scheduler
for this data snarfs this data and proceeds to the EXEC stage
(assuming all other operands were available).
In the response (RESP) pipeline stage, the data cache returns
hit/miss status and data for the request from DCACC.
AMD Athlon™ Processor x86 Code Optimization
145