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22007E/0—November 1999
MTRR MSR Format
Table 18. MTRR-Related Model-Specific Register (MSR) Map
Register Address
0FEh
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
250h
MTRRFIX64k_00000
258h
MTRRFIX16k_80000
259h
MTRRFIX16k_A0000
268h
269h
26Ah
26Bh
26Ch
26Dh
26Eh
26Fh
2FFh
Page Attribute Table (PAT)
This table defines the model-specific registers related to the
memory type range register implementation. All MTRRs are
defined to be 64 bits.
Register Name
MTRRcap
See "MTRR Capability Register Format" on page 174.
MTRR Base0
See "MTRRphysBasen Register Format" on page 183.
MTRR Mask0
See "MTRRphysMaskn Register Format" on page 184.
MTRR Base1
MTRR Mask1
MTRR Base2
MTRR Mask2
MTRR Base3
MTRR Mask3
MTRR Base4
MTRR Mask4
MTRR Base5
MTRR Mask5
MTRR Base6
MTRR Mask6
MTRR Base7
MTRR Mask7
MTRRFIX4k_C0000
MTRRFIX4k_C8000
MTRRFIX4k_D0000
See "MTRR Fixed-Range Register Format" on page 182.
MTRRFIX4k_D8000
MTRRFIX4k_E0000
MTRRFIX4k_E8000
MTRRFIX4k_F0000
MTRRFIX4k_F8000
MTRRdefType
See "MTRR Default Type Register Format" on page 175.
AMD Athlon™ Processor x86 Code Optimization
Description
185
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