AMD Athlon Processor x86 Optimization Manual page 229

22007E/0—November 1999
Table 22. Floating-Point Instructions (Continued)
Instruction Mnemonic
FCMOVB ST(0), ST(i)
FCMOVE ST(0), ST(i)
FCMOVBE ST(0), ST(i)
FCMOVU ST(0), ST(i)
FCMOVNB ST(0), ST(i)
FCMOVNE ST(0), ST(i)
FCMOVNBE ST(0), ST(i)
FCMOVNU ST(0), ST(i)
FCOM ST(i)
FCOMP ST(i)
FCOM [mem32real]
FCOM [mem64real]
FCOMI ST, ST(i)
FCOMIP ST, ST(i)
FCOMP [mem32real]
FCOMP [mem64real]
FCOMPP
FCOS
FDECSTP
FDIV ST, ST(i)
FDIV ST(i), ST
FDIV [mem32real]
FDIV [mem64real]
FDIVP ST, ST(i)
FDIVR ST, ST(i)
FDIVR ST(i), ST
FDIVR [mem32real]
FDIVR [mem64real]
FDIVRP ST(i), ST
FFREE ST(i)
FFREEP ST(i)
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
Instruction Dispatch and Execution Resources
First Second ModR/M
Byte Byte Byte
DAh C0-C7h
DAh C8-CFh
DAh D0-D7h
DAh D8-DFh
DBh C0-C7h
DBh C8-CFh
DBh D0-D7h
DBh D8-DFh
D8h 11-010-xxx
D8h 11-011-xxx
D8h mm-010-xxx DirectPath
DCh mm-010-xxx DirectPath
DBh F0-F7h
DFh F0-F7h
D8h mm-011-xxx DirectPath
DCh mm-011-xxx DirectPath
DEh D9h 11-011-001
D9h FFh
D9h F6h
D8h 11-110-xxx
DCh 11-111-xxx
D8h mm-110-xxx DirectPath
DCh mm-110-xxx DirectPath
DEh 11-111-xxx
D8h 11-110-xxx
DCh 11-111-xxx
D8h mm-111-xxx DirectPath
DCh mm-111-xxx DirectPath
DEh 11-110-xxx
DDh 11-000-xxx
DFh C0-C7h
AMD Athlon™ Processor x86 Code Optimization
Decode FPU
Type Pipe(s)
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath FADD
DirectPath FADD
FADD
FADD
VectorPath FADD
VectorPath FADD
FADD
FADD
DirectPath FADD
VectorPath
DirectPath FADD/FMUL/FSTORE
DirectPath FMUL
DirectPath FMUL
FMUL
FMUL
DirectPath FMUL
DirectPath FMUL
DirectPath FMUL
FMUL
FMUL
DirectPath FMUL
DirectPath FADD/FMUL/FSTORE
DirectPath FADD/FMUL/FSTORE
Note
1
1
1
1
1
1
1
1
1
1
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