Status Register Access Instructions; Load/Store Instructions - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.8.6

Status Register Access Instructions

Table 4-10. Status Register Access Instruction Timings
Instruction
MRS
MSR
4.8.7

Load/Store Instructions

Table 4-11. Load and Store Instruction Timings
Instruction
LDR
LDRB
LDRBT
LDRD
LDRH
LDRSB
LDRSH
LDRT
PLD
STR
STRB
STRBT
STRD
STRH
STRT
Table 4-12. Load and Store Multiple Instruction Timings
Instruction
†
LDM
STM
† See Table 4-4
†† numreg is the number of registers in the register list
Intel® PXA27x Processor Family Optimization Guide
Minimum Issue Latency
1
2 (6 if updating mode bits)
Minimum Issue Latency
1
1
1
1 (+1 if Rd is R12)
1
1
1
1
1
1
1
1
2
1
1
Minimum Issue Latency
††
2 + numreg
2 + numreg
for LDM timings when R15 is in the register list
Minimum Result Latency
2
1
Minimum Result Latency
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for Rd; 4 for Rd+1;
1 (+1 if Rd is R12) for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
N/A
1 for writeback of base
1 for writeback of base
1 for writeback of base
2 for writeback of base
1 for writeback of base
1 for writeback of base
Minimum Result Latency
5-18 for load data (4 + numreg for last register
in list; 3 + numreg for 2nd to last register in list;
2 + numreg for all other registers in list);
2+ numreg for writeback of base
2 + numreg for writeback of base
4-41