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System Level Optimization
This chapter describes relevant performance considerations that developers and system designers
should be aware of to efficiently use the Intel® PXA27x Processor Family (PXA27x processor).
3.1
Optimizing Frequency Selection
The PXA27x processor offers a range of combinations of core, system bus and memory clock
speed. The run mode frequency and derived system bus and memory controller frequencies affect
the latency and throughput of external memory interfaces.
Memory latencies depend on the run mode frequency, because a higher run mode frequency
improves performance for memory bound applications. The core clock speed is indicated by the
run frequency, or (if CLKCFG[T] is set) by the turbo frequency. This value is most significant for
computationally bound applications. For a memory bound application, a processor operating in
333-MHz run mode might perform better than a processor operating in 400-MHz turbo mode using
only a 200-MHz run mode frequency. The clock frequency combination should be chosen to fit the
target application mix. Possible frequency selections are listed in the clocks and power manager
section of the Intel® PXA27x Processor Family Developer's Manual.
3.2
Memory System Optimization
3.2.1
Optimal Setting for Memory Latency and Bandwidth
Because the PXA27x processor has a multi-transactional internal bus, there are latencies involved
with accesses to and from the Intel XScale® core. The internal bus, also called the system bus,
allows many internal operations to occur concurrently such as LCD, DMA controller and related
data transfers.
frequencies. The throughput reported in the tables is only measuring load
Table 3-1. External SDRAM Access Latency and Throughput for Different Frequencies
(Silicon Measurement Pending)
Core Clock
Speed (MHz)
(up to)
104
208
312
Intel® PXA27x Processor Family Optimization Guide
Table 3-1
and
Table 3-2
list latencies and throughputs associated with different
Run Mode
System Bus Clock
Frequency (MHz)
(up to)
104
208
208
Memory
Clock Speed
Speed (MHz)
(MHz)
(up to)
(up to)
104
104
208
104
208
104
3
Load
Memory
Throughput
Latency
from Memory
(core cycles)
(MBytes/
Sec)
17
205
21
326
30
343
3-1
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