Master Oscillator; Minor Vertical Expansion; Phase Counter - Raytheon DIDS-400 Series Technical Manual

Digital information display system terminal
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DIDS-402-2AM13
-1-18. 1 Master Oscillator
The master oscillatqr circuitry consists of oscillator transistor Q14,
crystal Xl, and saturated switch QIS.
The 2.4S76-MHz oscillator output is
used to provide master clock input for clocking the minor vertical expansion and
phase counter flip-flops.
4-18.2 Minor Vertical Expansion
The minor vertical expansion circuit functions as a divide-by-two counter
and is formed by flip-flop A26. 12.
The 1. 2288 (1. 3)-MHz output is coupled to the monoscope and CRT deflec-
tion circuits and is used to increase the height and clarity of characters displayed
on the CRT screen.
4-18.3 Phase Counter
The phase counte r consists of a second divide - by-two counter and is
formed by flip-flop A26. 9. ·By properly combining the master clock, minor
vertical, and phase counter outputs, four. phases of master clock are developed.
The phase counter produces outputs which occur in coincidence with the
fir st, se cond, third, and fourth maste r clock inputs.
The se inputs are commonly
known as phases 3,
1,
1, and 2, respectively.
An additional output, phase 12
(pronounced one-and-two), is produced by directly decoding the set output of the
phase counter flip-flop.
Internally, the phase counter outputs are used to enable circuit operation at
the beginning, middle or end of each bit.
The timing relationship is such that
the time span from phase 3 to phase 2 is equal to one bit time (see figure 4-19).
In the Display Terminal, gating functions required at the beginning of a bit are
accomplished during phase 3, while those at the end of a bit are accomplished
during phase 2.
The remaining phase counter outputs are used to perform. gating
during the center of a bit time.
The phase 2 output is used within the timing circuitry as a clock input to
the bit counter; thus, the bit counter is toggled at the end of each bit time.
ONE
~
BIT
l.-
I
TIME
I
MASTER CLOCK
l.flJUUlfUlJ1Jl
I
I
PHASE3~
I
I
PHASE4~
I
I
: n
I
n
PHASE I
....:.-_....1 ....... _ _ ,
L -
I
PHASE 2
'------'n"-_ _
fl
DIDS 68-518
Figure 4-19.
Phase Counter Outputs
4-44

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