Table of Contents
Advertisement
DIDS-402-2AM13
D3 continues to operate in this manner until an ETX character code is
shifted into D3 from the memory.
As discussed in paragraph 4-22. 1. 1, this
disable s the transmit operation by disabling T and returning all transmit/ receive
enable circuits to the receive (R) state.
When the Enter EOT wiring option is employed, an EOT character
(0000100) is inserted as the last character of the rn.e ssage rather than an ETX
(0000011).
To accorn.plish this, the wire connecting terminals AA and AB is
rern.oved to place a constant high at one input of NAND-gate A26. B.
When SG23
goes high during transmit to indicate a D2 to D3 transfer, the second input of
A26. B is enabled every 4{CTS+l).
If the character entered into D3 by SG23 was
an ETX, the ETXD3 decode is enabled during 3CTS.
This sets AlB. 3 and enables
4{CTS+l) to be gated through to reset the two LSB's of D3 and to set the third LSB.
In this manner, a code conversion is accorn.plished and EOT is transmitted to the
CPU instead of ETX.
4-22.4.4 Escape and Communications Control Code Flip-Flops
The ESC and CCC flip-flops and their associated circuits are shown in
figure 4-35.
ESC codes are used in rn.essages from the CPU to enable the
storage of the following control codes;
CAN
DC3
DCI
CR
FF
VT
HT
BS .
ETX
ESC
When one of the preceding control codes is received irn.rn.ediately after an
ESC code, the specified edit or cursor control function is not perforrn.ed and the
control code is perrn.itted to enter the delay-line mern.ory.
Conyer sely, if the
code is received without being preceded by ESC, the specified function is per-
forrn.ed but the code is not permitted to enter the delay-line rn.ern.ory.
The
circuit shown in figure 4-35 perforrn.s this function in the following manner.
Norrn.ally, a high is present at the reset output of the CCC and ESC
flip-flops.
When the Display Terrn.inal is in the receive rn.ode (RE=HIGH),
A15.6 goes high once per character during 4(CTS+1).
4-93
Advertisement
Chapters
Table of Contents
