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DIDS-402-2AMI3
In the enquiry-response conversational mode, the ENQ option is employed
by connecting a wire between terminals PF and PE.
When ENQ is decoded in
buffer register D3, a low at the output of NAND-gate A24. 8 is used to set
ENQ-flip-flop AI. 3 to produce a low at AI. 6.
As shown in figure 4-24, this low
simulate s depressing XMIT and if an ETX code is found in the memory loop,
the receive (R) function is disabled.
Transmis sion then occur s in the usual
manner by sequentially entering STX and DA into the buffer registers and then
enabling data transfers from the delay line.
4-22.2 Receive-Enable
The display terminal receive enable circuitry is shown in figure 4-26.
As stated previously in transmit enable, the receive logic is enabled when the
Display Terminal is not actively transmitting.
This factor allows data to be
shifted into buffer register DI from the CPU.
The received data, however, is not
permitted to enter buffer register D2 until STX and DA are received sequentially.
These two character s are detected by decodes connected to buffer register DI.
4-22.2. I Enquiry-Re sponse
In the enquiry-response conversational mode, the Display Terminal may
receive either a solicited or an unsolicited response from the CPU.
Normally,
the Display Terminal is awaiting a respons.e to a previously transmitted enquiry.
The STX and ADDR flip-flops are reset by any of the inputs to NOR-gate A63. 6.
When the STX character code is received from the CPU, the Display
Terminal interprets the code as the beginning of a response.
Even though the
message may not be intended for use by any particular Display Terminal, all
display terminals connected to the CPU respond by entering the receive enable
sequence.
STX decode A 75.8 produces a low output which simuitaneously sets
STX flip-flop A79.12 and resets ADDR flip-flopA79. 9.
This enables AND-gate
A81.8 and places a high at the inputs to NAND-gates A 71. 3 and A82. 6.
With
the STX flip-flop set, the circuit idles until the next character is received.
If the next character received is the correct address (either display
address or broadcast address), NAND-gate A82.6 is enabled and the resulting
output sets ADDR flip-flop A 79.9.
When both the STX and ADDR flip-flops are
set, NAND-gate A 78.6 is enabled to develop a receive enable (RE) output.
This
output is used to permit all characters following DA to enter buffer registers D2
and D3.
From buffer register D3, the characters enter the refresh memory loop
at the character entry register and are displayed on the CRT screen.
When ETX
is decoded in D3, the ETXD3 output enables one input to NOR-gate A63. 6 and the
STX and ADDR flip-flops are jammed reset.
This removes both inputs from
NAND-gate A 78.6 and the receive operation is terminated.
If the character following STX is the improper address. NAND-gate A82. 6
is not enabled.
The high output is coupled to A 71. 3 and the resulting low is
coupled via strapping terminals CG and CF to the reset inputs of the STX and
ADDR flip-flops.
On the next clock pulse, both flip-flops are reset and the
circuit returns to its quiescent state.
4-63
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